It is a significant trend of designing the integrated circuits (“ICs”) to have smaller size and increased density. To this end, in terms of packaging the ICs, flip chip packaging approach is more and more popularly used instead of the traditional wire bonding solutions.
In the flip chip packaging approach, conductive bumps (e.g. solder bumps, copper bumps, copper pillar with solder bumps etc.) are used to couple electrical terminals of an IC device to a package lead frame, a package substrate or a circuit board. The IC device may comprise a semiconductor substrate with active or passive circuit elements and connections formed on it, and may generally have tens or hundreds of electrical terminals, either input or output or input and output terminals, for receiving or sending signals or for coupling to power supply connections. Conventionally, a group of the electrical terminals with the similar or the same functions, e.g. the ones needing to be coupled to a power supply, are coupled together to a dedicated pad formed in a top metal layer on the semiconductor substrate. A protective insulting layer, called a passivation layer is then formed to overlie the top metal layer with an opening formed in the passivation layer to expose the dedicated pad for each group of the electrical terminals. Subsequently, a conductive bump may be formed on the passivation layer over the dedicated pad and be connected to the dedicated pad through the opening. In this fashion, a connection route is formed from each group of the electrical terminals having the similar or the same functions to the corresponding conductive bump. However, such a connection route has a significant connection resistance with limited current handling capability and may not be able to meet the practical application requirements, especially in high current applications.
Furthermore, as the size of the IC device continues to fall and the density continues to increase, connecting a group of the electrical terminals with the similar or the same functions to their dedicated pad becomes more and more difficult and the connection routing is complex and hard to design within the top metal layer on the semiconductor substrate, making the design and connection of the electrical terminals inflexible.
In addition, after the conductive bumps for all groups of the electrical terminals are prepared, a thermal reflow process may then be used to make the conductive bumps to at least partially melt and then reflow to complete a mechanical and electrical connection between the integrated circuit and a package lead frame, a package substrate or a circuit board via the conductive bumps. However, since the pitch between different electrical pads of the IC device is decreasing. In consequence, conductive bumps corresponding to the different electrical pads may bridge due to migration of the melted conductive bumps during the thermal reflow process, causing electrical shorts.
Moreover, delamination of a molding compound, generally formed to wrap and mold the package, from die surface may occur when the IC device operates under certain extreme operating conditions, especially under high temperature and high humidity conditions, which may also leading to failure of the IC device when operating in such extreme operating conditions.
A need therefore exists in reducing the interconnection resistance and improving the current handling ability, quality and reliability of a semiconductor device using conductive bumps and requiring size reduction.